1. Field of the Invention
The present invention relates to a resin-encapsulated semiconductor device with a lead frame. Particularly, it relates to a structure that is suitable for achieving the reduction in thickness and the increase in speed of elements, and a structure that is employed for achieving three-dimensional mounting of a plurality of resin-encapsulated semiconductor devices, in a resin-encapsulated semiconductor device called SIP (System In Package). Furthermore, the present invention relates to a lead frame used therein and the method of producing the same as well as the method of producing a resin-encapsulated semiconductor device.
2. Related Background Art
Conventionally, a resin-encapsulated semiconductor device called “QFN (Quad Flat Non-leaded Package)”, only one side of which is encapsulated with an encapsulating resin, has been developed as a compact and thin resin-encapsulated semiconductor device. The following will describe the conventional QFN-type resin-encapsulated semiconductor device.
First of all, the following describes a lead frame used in a resin-encapsulated semiconductor device. FIG. 6 is a plan view illustrating a conventional lead frame 1. This lead frame 1 has a structure in which a die pad 4 arranged substantially at the center of an opening region 3 of a frame 2 is supported by hanging leads 5. One end of each of the hanging leads 5 is connected with each of the corners of the die pad 4, while the other end thereof is connected with the frame 2. Further, the frame 2 is provided with a plurality of inner leads 6, which are arranged so that their ends face corresponding edges of the die pad 4.
Next, the following describes a conventional resin-encapsulated semiconductor device employing the foregoing lead frame. FIGS. 7A and 7B show a conventional resin-encapsulated semiconductor device. FIG. 7A is a bottom view of a resin-encapsulated semiconductor device, and FIG. 7B is a cross-sectional view of the device taken along line A–A1 shown in FIG. 7A. A semiconductor chip 7 is bonded to the die pad 4, and the frame 2 of the lead frame 1 (see FIG. 6) is cut away, so that the inner leads 6 are separated from one another. Electrodes 8 of the semiconductor chip 7 are connected electrically with the surfaces of the inner leads 6 through thin metal wires 9, respectively. The surroundings of the semiconductor chip 7 are encapsulated with an encapsulating resin 10, with the bottom face of the die pad 4 and the bottom faces of the inner leads 6 being exposed. The bottom faces and side faces of the inner leads 6 are exposed at a bottom face and side faces of the package 11, respectively, thereby forming external terminals 12.
Next, the following describes a method of producing the resin-encapsulated semiconductor device shown in FIGS. 7A and 7B. FIGS. 8A to 8E illustrate steps of the production method by showing, like FIG. 7B, the cross-sections taken along line A–A1 indicated in FIG. 7A.
First, a lead frame 1 is prepared as shown in FIG. 8A. This lead frame 1 is the same as that shown in FIG. 6, though the illustration of the frame 2 (see FIG. 6) is omitted therein. The drawing shows a die pad 4 on which a semiconductor chip is to be mounted, and one of a plurality of inner leads 6 arranged so that their ends face the corresponding edges of the die pad 4. Next, as shown in FIG. 8B, a semiconductor chip 7 is mounted on the die pad 4 of the lead frame 1 by bonding. Then, as shown in FIG. 8C, the semiconductor chip 7 is connected electrically with surfaces of the inner leads 6 through thin metal wires 9.
Subsequently, as shown in FIG. 8D, the surroundings of the die pad 4, the surfaces of the inner leads 6, and the semiconductor device 7 are covered with a molding die 13 to be encapsulated with an encapsulating resin. Thereafter, as shown in FIG. 8E, the package 11 that has been encapsulated with the encapsulating resin 10 is taken out of the molding die. Thus, a resin-encapsulated semiconductor device is completed in which the bottom faces and outer side faces of the inner leads 6 are arranged in the bottom of the package 11 to serve as external terminals 12 (see, for instance, JP2000-307049A).
However, the conventional resin-encapsulated semiconductor device as described above is very thick as a whole since the thin metal wires are used for connecting the electrodes of the semiconductor chip with the inner leads, and hence, there are limits to the reduction in thickness of the device. Furthermore, since no consideration has been given to the size of the exposed faces of the inner leads that form the external terminals, the above-mentioned structure was not suitable for reducing the size of the external terminals and the pitch of the external terminals, i.e. the distance between the external terminals.
In addition, in a situation where high-speed signals or high-frequency signals operate, loss of signals in the thin metal wires becomes a problem, which prevents the semiconductor chip from fully functioning.
Moreover, since the external terminals are exposed only at the bottom face of the resin-encapsulated semiconductor device, when a plurality of resin-encapsulated semiconductor devices are stacked on top of each other, no electric connection can be established between the devices through their external terminals. Thus, it is difficult to implement the three-dimensional packaging.